The increasing design of high-frequency signals is closely tied to the steady enhancement of electronic system performance. PCB designers face mounting challenges as system performance improves: smaller die sizes, denser board layouts, and lower power consumption chip requirements. Technological advancements always come with a series of issues. With the boost in system performance and the adoption of high-speed designs, some problems must be addressed within the design environment.
Below, we summarize the challenges faced:
Signal Quality
IC manufacturers are leaning towards lower core voltages and higher operating frequencies, sharply increasing edge rates. Edge rates in unterminated designs can cause reflections and signal quality issues.
Crosstalk
In high-speed signal designs, dense pathways often lead to crosstalk—the electromagnetic coupling phenomenon between traces on a PCB. Crosstalk can be edge coupling on the same layer or broadside coupling on adjacent layers. Coupling is three-dimensional. Compared to side-by-side trace routing, parallel routing, and broadside traces cause more crosstalk.
Broadside Coupling (Top) vs. Edge Coupling (Bottom)
Radiation
Rapid edge rates in traditional designs, even with the same frequencies and trace lengths as before, can generate ringing on unterminated transmission lines. This fundamentally leads to higher radiation, far exceeding the FCC/CISPR Class B limits for unterminated transmission lines.
10ns (Left) and 1ns (Right) Edge Rate Radiation
Design Solutions
Signal and power integrity issues can intermittently arise and are difficult to discern. Therefore, the best approach is to identify and eliminate the root causes during the design process rather than attempting to resolve them in later stages, which can delay production. Using stack-up planning tools can make it easier to implement solutions for signal integrity issues in your design.
Board Stack-Up Planning
The top priority for high-speed designs is the board stack-up. The substrate is the most critical component in the assembly, and its specifications must be meticulously planned to avoid discontinuous impedance, signal coupling, and excessive electromagnetic radiation. When reviewing the board stack-up for your next design, keep in mind the following tips and recommendations:
- All signal layers should be adjacent and tightly coupled to an uninterrupted reference plane, which creates a defined return path and eliminates broadside crosstalk.
Each Signal Layer's Substrate Adjacent to a Reference Plane
- Have good planar capacitance to reduce AC impedance at high frequencies. Tightly coupled internal power plane pairs reduce AC impedance on the top layer, significantly minimizing electromagnetic radiation.
- Reducing dielectric height greatly reduces crosstalk without impacting the board's available space.
- The substrate should accommodate a range of different technologies. For example 50/100-ohm digital, 40/80-ohm DDR4, 90-ohm USB.
Routing and Workflow
After meticulously planning the stack-up, the next step is to focus on board routing. Based on carefully configured design rules and work areas, you can route the board efficiently and successfully. These tips will help make your routine easier and avoid unnecessary crosstalk, radiation, and signal quality issues:
- Simplify views to clearly see split planes and current loops. To do this, first, determine which copper foil plane (ground or power) serves as the reference plane for each signal layer, then open the signal layer and internal power plane for simultaneous viewing. This helps you more easily see traces on split planes.
Multiple Signal Layers (Left), Top Layer and Adjacent Plane View (Right)
- If digital signals must cross power reference planes, you can place one or two decoupling capacitors (100nF) close to the signal. This provides a current return path between the two power supplies.
- Avoid parallel and broadside routing, which causes more crosstalk than side-by-side routing.
- To reduce crosstalk, keep parallel segments as short as possible unless using synchronous buses. Allow space for signal groups, with address and data spacings three times the trace width.
- Be cautious when using combined microstrip layers on the top and bottom of the board. This can cause crosstalk between traces on adjacent layers, jeopardizing signal integrity.
- Route clock (or strobe) signal traces based on the longest delay of the signal group, ensuring data is established before the clock reads it.
- Routing embedded signals between planes helps minimize radiation and provides ESD protection.
